1. Field of the Invention
This invention relates generally to computer system clocks, and, more particularly, to synchronizing clock signals using a slave variable delay loop.
2. Description of the Related Art
Modem high performance computer systems comprise a plurality of electrical devices such as processors and memory controllers that are typically controlled by derivatives of a common reference clock signal. The reference clock signals must be synchronized at locations within the system, if the system is to function optimally. However, even though the individual reference clock signals may have a common source, they often do not arrive at their intended destination in proper synchronism due to flight time mismatches. For example, the electrical devices receiving the clock signal may be located at various distances from the common reference clock, causing the reference clock signals to reach the electrical devices at different times.
Synchronization involves aligning the clock edges (i.e. "de-skewing" or matching phases) of an on-chip receiver clock signal with a reference clock signal. Conventionally, a phase-lock loop (PLL) or a delay-lock loop (DLL) are utilized to align the edges of a receiver (or a driver) clock signal with a reference clock signal. Both PLLs and DLLs are well known in the art and, thus, their structure and operation will be apparent to persons skilled in the relevant art.
FIG. 1 illustrates a prior art method that utilizes PLLs 5,10 to align a first and second feedback input clock signals (also known as the channel 1 and 2 clock signals, respectively) 12,14 with the respective reference clock signals 15,20. As shown, a common source clock 25 generates the reference clock signals 26,28 that are coupled to the respective left and the right memory channels 30,35, which, for example, may be channels of a bank of dynamic random access memory (DRAM) chips. The left memory channel 30 is coupled to a first input/output (I/O) channel 40 of a device (i.e. a memory controller, for instance) 45, while the right memory channel 35 is coupled to a second I/O channel 50 of the device 45.
Because of the flight time mismatches, it is possible for the reference clock signal 26 and the reference clock signal 28 to be out of phase with respect of each other when they arrive at the device 45. For clarity, a left reference clock signal 15 is denoted to represent the reference clock signal 26 after it propagates through the left memory channel 30 and arrives at the first channel 40 of the device 45. Likewise, a right reference clock signal 20 represents the reference clock signal 28 at the second channel 50 of the device 45. The left and right reference clock signals 15,20 are input into the first I/O channel 40 and second I/O channel 50, respectively, and are further coupled to the input terminals of the respective PLLs 5,10.
The PLLs 5,10 typically include a phase detector (not shown) and a voltage controlled oscillator (VCO) (not shown) that generates a receiver clock signal 52,54. The phase detector of the PLLs 5,10 compares the phase of the channel 1 and channel 2 clock signals 12,14 with the phase of the respective reference clock signals 15,20. The output of the phase detector is then used to control the VCO, which generates a clock signal 52,54 so that the channel 1 and channel 2 clock signals 12,14 are substantially aligned with the respective reference clock signals 15,20. Once this phase alignment has occurred, the phase relationship between the reference clock signals 15,20 and the respective channel 1 and channel 2 clock signals 12,14 is referred to as being "locked." It is possible to have a plurality of clock buffers 60, 65 in a feedback loop of the PLLs 5,10.
Those skilled in the art will appreciate that DLLs (not shown) can be utilized in lieu of the PLLs 5,10 in FIG. 1. A DLL differs from a PLL 5,10 in that a voltage controlled delay (VCD) (not shown) is used instead of a voltage controlled oscillator (VCO) (not shown). Like the PLL 5,10, the DLL is capable of receiving two input signals and then "locking" the phases of the two signals.
While both PLL 5,10 and DLL (not shown) are capable of synchronizing the phases of the channel 1 and channel 2 clock signals 12,14 with the respective phases of the reference clock signals 15,20, they still suffer from several shortcomings. A PLL 5,10 and DLL not only require substantial amounts of power for operation but also require a large estate (i.e. die size) on the device 45. The limited amount of power and space available on a device 45 becomes especially critical in situations where the device 45 has multiple input/output channels 40,50, where each I/O channel 40,50 requires a PLL 5,10 or DLL to synchronize the incoming reference clock signal 15,20 with a receiver clock signal. Thus, what is needed is a method and apparatus for synchronizing clock signals that demand less power and can be housed on a smaller die.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.